#Technical studies – Study 19
A clamper is a circuit that adds a dc voltage to the input ac signal. It can shift the ac signal either up or down up to a dc level. Clamper circuits are widely used in television receivers, radars and communication circuits to change the reference level of the signals.
Positive clamper circuit:
A positive clamper is a circuit that shifts the input signal to upside of the zero level. Below drawing shows the circuit of a positive clamper.
The circuit has a diode, capacitor and a load resistor. As a capacitor is available in the circuit it will have a charging and a discharging time. So the time constant τ is assumed to 100 times greater than the time period of the input signal.
τ = RC > 100 T ( Time period of input signal)
The clamper circuit that obeys this rule is called stiff clamper.
In the circuit during the positive half cycle of the signal the diode is off, so the capacitor is off. During the negative half cycle of the signal diode is on, so the capacitor starts charging up to the Vp.
Again during positive half cycle the capacitor remains in full charge, because the time constant is greater than the signal time period and acts as a battery with a voltage of Vp. The capacitor voltage adds to the input signal and appears across the output. So the output waveform is shifted to up side of the zero level. The clamping level starts after -0.7 V as the diode drops 0.7 V during conduction.
Negative clamper circuit:
If we change the polarity of diode and capacitor in the circuit of positive clamper, it will become negative clamper. Negative clamper shifts the signal to down side of the zero level. Below drawing shows the circuit of a negative clamper.
In circuit during positive half cycle of the signal the diode is on so the circuit acts as a short circuit. The capacitor starts charging up to the Vp level. As current flows through diode, there is no output.
During negative half cycle the diode is off. The capacitor acts like a battery with the voltage of Vp. The capacitor voltage gets added to the input signal and appears across the output. So the output waveform shifts to down side of the zero level. The clamping level starts after 0.7 V as the diode drops 0.7V during conduction.
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